1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for rapidly and accurately trimming the values stored by reference cells used for reading flash EEPROM memory.
2. History of the Prior Art
Recently, flash electrically-erasable programmable read only memory (flash EEPROM memory) has been used as a new form of long term storage. A flash EEPROM memory array is constructed of floating gate field effect transistor devices. Such memory transistors may be programmed by storing a charge on the floating gate. The condition (programmed or erased) may be detected by interrogating the cells. An example of a flash EEPROM memory array which may be used in place of a hard disk drive is given in U.S. patent application Ser. No. 07/969,131, entitled A Method and Circuitry For A Solid State Memory Disk, S. Wells, filed Oct. 31, 1992, and assigned to the assignee of the present invention. These arrays provide a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage. Such memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important.
Recently, it has been discovered that the transistor devices used for flash EEPROM memory arrays may be made to store more than two conditions. Essentially, four or more distinct levels of charge may be stored on the floating gate of the devices by varying the voltages applied to the terminals of the devices; and these different levels may be detected. This allows flash EEPROM devices in memory arrays to store more than one bit per device and radically increases the storage capacity of such arrays.
Flash EEPROM arrays, like other transistor memory arrays utilize reference devices to store values against which the memory cells are tested to determine their condition when the memory cells are read. These reference devices are typically flash EEPROM devices similar to those used for storing data in the array. In a typical memory array in which two possible conditions are available for each memory cell, the reference devices are programmed into a condition to produce a particular current value when interrogated which is midway between the two conditions of the memory cells. The current through the reference device in turn produces a voltage which is measured against a voltage produced by current through a memory cell. The condition of the reference device need not be programmed especially accurately because there is a large margin for error between the two states of the memory cells which the reference device is used to measure. Consequently, this condition has normally been programmed using gate and drain voltages unrelated to operation of the array to obtain a desired current value through the reference devices. Typically, this programming has been a relatively slow process due to the need to program and test repeatedly until a correct current is realized.
With the new storage arrangements in which more than one bit may be stored by each memory transistor, many more reference cells are utilized since many more levels must be tested to determine a value stored by the floating gate of a memory cell. Since a number of voltage levels must be measured, the values stored by the reference cells need to be very accurately determined. It would be useful if this could be accomplished by a process which could be rapidly consummated.